Joint webinar, FirstTo6G and 6G-REFERENCE

Following the successful webinar that we organised with our SNS sister project, 6G-REFERENCE, last January, we are pleased to announce a second edition.

The microelectronics hardware concepts and the resulting research of both projects complement each other, and we share the same SNS-JU stream: 'B-01-05: Microelectronics-based Solutions for 6G Networks'.

We will present some of the most notable results from both projects, followed by an open discussion about our approaches and the synergies between these two SNS projects, and potentially others.

 

Agenda of the webinar

ItemSpeaker
All times are in CET
15.00Welcome, agenda overview and goalsRenato Negra – RWTH, moderator
15.10Millimeter-Wave RF Front-End Design in 22 nm FDSOI Technology for Next-Generation 6G CommunicationMartin Wiezell, Sivers Semiconductors
15.30A 20 GHz Direct Crystal Sinewave Sampling Fractional-N PLLErwin Hardeveld, University of Twente
15.50Time and Direction of Arrival Estimation under Interference and Multipath: Robustness and Super-Resolution via Spatial FilteringAntónio Barros, ETHZ
16.10RapidIP, an algorithm-based automated design and synthesis tool used for rapid generation of RF (Radio Frequency) and microwave power amplifiersEduard Heidebrecht, RapidRF
16.30Panel discussion with all speakersModerator: Renato Negra, RWTH
17.00End of the webinar
 
Renato Negra, RWTH
Renato Negra received the M.Sc. degree in Telematics from Graz University of Technology, Graz, Austria, and the Ph.D. degree in Electrical Engineering from ETH Zürich, Zürich, Switzerland. Before joining ETH Zürich for PhD research on power-efficient linear amplification, he was involved in the design and characterisation of space-qualified RF equipment as development engineer at Alcatel Space Norway AS. His PhD research at the Laboratory for Electromagnetic Fields and Microwave Electronics at the ETH Zürich was focused on power-efficient linear amplification of wireless communication signals. Afterwards he was a Post-Doctoral Fellow at the iRadio Lab, University of Calgary, Canada, working on switching-mode power amplifiers and advanced wireless transmitter architectures. He became Assistant Professor for Mixed-Signal CMOS Circuits at RWTH Aachen University (2008), and a Full Professor for High Frequency Electronics (2013). His research interests are high frequency circuits and systems in silicon, III-V, and 2D-material technologies. Particular interests include power amplifiers and transmitter architectures, as well bendable electronics. He is co-founder of 4 deep-tech start-ups which all are based on research results of the Chair of High Frequency Electronics.
Martin Wiezell, Sivers Semiconductors
Martin Wiezell received the M.Sc. and Ph.D. degrees from KTH Royal Institute of Technology, Sweden, in 1996 and 2001, respectively. He was a Visiting Scholar at McMaster University, Canada, during 2000-2001. He has more than 20 years of experience in RFIC design. Since 2021, he has been with Sivers Semiconductors, where he develops RF front-end solutions for next-generation millimeter-wave transceivers in advanced RF-SOI technologies. Prior to joining Sivers, he held principal RFIC design positions at Spirea, DiBcom, Parrot, and Faurecia Clarion. His work has focused on the development of RF-CMOS circuits and receiver architectures for Bluetooth, WLAN, television, automotive, LTE, and IoT applications. As a co-founder of DiBcom's Swedish design center, he led the development of low-power RF receiver architectures and was responsible for the top-level integration and tape-out of multiple IC generations that were successfully transferred to high-volume production. He is the inventor of four patents, has authored more than 20 scientific publications, and contributed to a book chapter on low-frequency noise modeling in advanced semiconductor devices.
Erwin Hardeveld, University of Twente
Erwin Hardeveld received the M.Sc. degree in electrical engineering from the University of Twente, Enschede, The Netherlands, in 2018. He is currently pursuing the Ph.D. degree with the Integrated Circuits Design Group within the context of the 6G-Reference project. His research interests include RF receiver front-ends, time synchronization, and phase-locked loops.
António Barros, ETHZ
António Barros is a PhD researcher in the Integrated Information Processing (IIP) group at ETH Zürich, led by Prof. Christoph Studer, and holds a Master's degree from the University of Porto, Portugal. His interests lie in signal processing and machine learning for wireless communication, with an emphasis on modeling the effects of hardware impairments and harsh propagation environments, and on designing synchronization, sensing, and transceiver algorithms that are robust to them. His work spans theory, simulation, and experimentation with software-defined radios and a 5G testbed.
Eduard Heidebrecht, RapidRF
Eduard Heidebrecht is the Co-Founder of RapidRF, a deep-tech company transforming radio frequency integrated circuit (RFIC) design through AI-driven automation. By converting RF design specifications into tapeout-ready layouts in hours rather than months, RapidRF eliminates traditional engineering bottlenecks, drastically reduces development costs, and accelerates time-to-market—all while ensuring clients retain full IP ownership. Driven by a vision to make RF development as scalable and agile as modern software engineering,he focuses on empowering the next generation of wireless, aerospace, radar, and communication technologies. An active collaborator within the semiconductor ecosystem, he regularly engages with design teams, infrastructure providers, and deep-tech investors to drive automated hardware innovation.
 

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FirstTo6G has received funding from the Smart Networks and Services Joint Undertaking (SNS JU) and its members under the European Union’s Horizon Europe programme and by the Swiss State Secretariat for Education, Research and Innovation (SERI).

Views and opinions expressed are those of the author(s) only and do not necessarily reflect those of the European Union, SNS JU or SERI. Neither the European Union nor the granting authorities can be held responsible for them.

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